A bit about us:
A security processor company redefining hardware root of trust with hardware-based security technologies, including per-system AI.
Why join us?
Great product working on Security system processors and is an AI-powered engineer to prevent hackers. Great equity options based on experience, and working with a strong team in the bay area.
ASIC/ SOC designer- RTL logic design and implementation, microarchitecture, timing closure, coding in verilog
Big plus for embedded CPU design.
Onsite in San Jose, California. Full Job description below.
Help develop the design and implementation of SoCs;
Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
Top-level and block-level performance, bandwidth, power, and cost analysis and optimization;
Work with FPGA engineers to perform early prototyping; and
Support test program development, chip validation, and chip life until production maturity.
Team Management and Building
Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
5+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
Proficient in writing clear, implementable micro-architecture specifications;
Expertise in writing efficient RTL code in Verilog;
Good understanding of assertions, coverage analysis, synthesis, and timing closure;
Experience in revision control, regression, and bug-tracking tools;
Fluency with scripting languages (e.g., Perl, Python);
Must have gone through at least one tape out;
Preferred: Lab debug/bring-up experience
BA or MS (preferred) degree in EE/EECS/CS or equivalent.